1. Field of the Invention
The present invention relates to a signal transmission technology and, more particularly, to a receiver, a transceiver circuit, a signal transmission method, and a signal transmission system for performing high-speed signal transmission between LSI chips or between a plurality of devices or circuit blocks accommodated on the same chip, or between boards or enclosures.
2. Description of the Related Art
In recent years, the performance of components used to construct computers and other information processing apparatuses has improved greatly; for example, performance improvements for semiconductor memory devices such as DRAM (Dynamic Random Access Memory) and processors and the like have been remarkable. The improvements in the performance of semiconductor memory devices, processors, etc. have come to the point where system performance cannot be improved further unless the speed of signal transmission between components or elements is increased.
For example, the speed of signal transmission between a main storage device such as a DRAM and a processor is becoming a bottleneck impeding performance improvement for a computer as a whole. The need for the improvement of signal transmission speed is increasing not only for signal transmission between enclosures or boards (printed wiring boards), such as between a server and a main storage device or between servers connected via a network, but also for signal transmission between. LSI (Large Scale Integration) chips or between devices or circuit blocks accommodated on the same chip because of increasing integration and increasing size of semiconductor chips, decreasing supply voltage levels (signal amplitude levels), etc.
Specifically, there is a need to increase the signal transmission speed per pin in order to address the increase in the amount of data transmission between LSIs or between boards or enclosures. This is to avoid an increase in package cost, etc. due to increased pin count. As a result, the inter-LSI signal transmission rate in recent years has exceeded 1 Gbps, and in the future (three to eight years from now) it is expected to reach an extremely high value (very high signal transmission rate) such as 4 Gbps or even 10 Gbps.
It is thus desired to provide a transceiver circuit that can evaluate and diagnose signal transmission systems, optimize transmission/reception parameters, and achieve increased receiver sensitivity, and also a receiver that can eliminate a large common mode voltage in a circuit used for signal transmission.
For signal transmission between boards or enclosures, between LSI chips, or between a plurality of devices or circuit blocks accommodated on the same chip, there is a need to increase the efficiency of use of a transmission line by reducing the number of signal lines, wiring patterns, etc. and, in view of this, it is also desired to provide a signal transmission system, a signal transmission method, and a transceiver circuit capable of providing higher-accuracy and higher-speed signal transmission in both directions.
The prior art and its associated problem will be described in detail, later, with reference to the accompanying drawings.
A first object of the present invention is to provide a transceiver circuit that can evaluate and diagnose signal transmission systems, optimize transmission/reception parameters, and enhance receiver sensitivity. It is also an object of the present invention to provide a receiver that can eliminate a large common mode voltage in a circuit used for signal transmission.
A second object of the present invention is to provide a receiver capable of achieving higher-accuracy and higher-speed signal transmission by allowing a large timing margin for the operation of a decision circuit.
A third object of the present invention is to provide a signal transmission system, a signal transmission method, and a transceiver circuit that can achieve more efficient utilization of the signal transmission line and accurately perform high-speed signal transmission using fewer signal lines, and that can extend the maximum signal line length.
According to the present invention, there is provided a receiver comprising an offset application circuit for applying a known offset to an input signal; and a decision circuit for comparing the offset-applied input signal with a reference voltage, wherein the level of the input signal is determined based on the known offset and on a result output from the decision circuit.
The offset application circuit may include an offset level control circuit for controlling the level of the offset by a digital signal. The receiver may further comprise an input signal level detection circuit for detecting the level of the input signal by increasing or decreasing the level of the offset using the offset level control circuit, and by finding an offset level where the result output from the decision circuit changes. The receiver may further comprise a timing control circuit for controlling decision timing in the decision circuit in such a manner as to vary the decision timing relative to an internal clock in the receiver, and wherein the level of the offset is adjusted by judging an externally supplied, predetermined test pattern at output timing of the timing control circuit, and information concerning the input signal is acquired using the input signal level detection circuit.
The offset voltage application circuit may pass a constant current to a termination resistor provided in parallel to an input terminal of the receiver. The offset voltage application circuit may include a plurality of capacitors and switches, and vary the level of the offset by varying a precharge voltage of each of the capacitors. The offset voltage application circuit varies the level of the offset by passing a constant current into an internal node in the receiver. The offset voltage application circuit varies the level of the offset by passing a constant current into an internal node in the receiver. The received signal quality of the input signal may be diagnosed, or a characteristic of the receiver or driver may be adjusted, by using the waveform of the input signal obtained from the known offset and the result output from the decision circuit.
Further, according to the present invention, there is provided a transceiver circuit having a receiver for receiving a signal input thereto, and a driver for outputting a signal, wherein the receiver comprises an offset application circuit for applying a known offset to the input signal; and a decision circuit for comparing the offset-applied input signal with a reference voltage, wherein the level of the input signal is determined based on the known offset and on a result output from the decision circuit.
According to the present invention, there is also provided a signal transmission system having a first transceiver circuit, a second transceiver circuit, and a signal transmission line connecting between the first and second transceiver circuits, wherein each of the transceiver circuits comprises a receiver for receiving a signal input thereto, and a driver for outputting a signal; and the receiver includes an offset application circuit for applying a known offset to the input signal and a decision circuit for comparing the offset-applied input signal with a reference voltage, wherein the level of the input signal is determined based on the known offset and on a result output from the decision circuit.
A predetermined test pattern may be transmitted from the driver in the first transceiver circuit, the test pattern may be judged at predetermined timing using the receiver in the second transceiver circuit; and the level of the test pattern may be detected by adjusting the level of the offset in the second transceiver circuit, thereby adjusting an equalization parameter of the receiver in the second transceiver circuit. A boundary signal which should be judged to be at a boundary between data xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d may be transmitted to the receiver in the second transceiver circuit by the driver in the first transceiver circuit; the boundary signal may be received by the receiver in the second transceiver circuit and such a boundary offset may be sought that the result of a decision in the decision circuit of the receiver agrees with the boundary between data xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d; and zero adjustment of the receiver in the second transceiver circuit may be performed by applying the boundary offset to the receiver at the time of usual input signal reception.
A predetermined test pattern may be transmitted to the receiver in the first transceiver circuit by the driver in the first transceiver circuit; and the test pattern may be received by the receiver in the second transceiver circuit by sequentially changing receive timing in the receiver and the level of the test pattern may be detected, thereby adjusting a parameter of the second transceiver circuit.
In addition, according to the present invention, there is provided a receiver having a plurality of signal lines and a capacitor network having capacitors connected to the signal lines and switches for controlling the connection of the capacitors, wherein the receiver includes a common mode voltage elimination circuit for eliminating a common mode voltage present on the plurality of signal lines by connecting at least one of capacitor nodes containing the component of the common mode voltage to a node held to a specific voltage value.
According to the present invention, there is provided a receiver comprising a plurality of signal: lines and a capacitor network having capacitors connected to the signal lines and switches for controlling the connection of the capacitors, wherein the receiver includes a common mode voltage elimination circuit for eliminating a common mode voltage present on the plurality of signal lines by connecting at least one of capacitor nodes containing the component of the common mode voltage to a node precharged to a specific voltage value.
The common mode voltage elimination circuit may include a corresponding voltage generating circuit for generating a voltage value corresponding to the common mode voltage, and a capacitor charging circuit for charging one end of the capacitor by the output voltage of the corresponding voltage generating circuit. The common mode voltage elimination circuit may include a difference voltage capacitor charging circuit for charging an input capacitor by a difference voltage appearing on the plurality of signal lines, and a connection control circuit for connecting a terminal of the input capacitor to an input terminal of a decision circuit subsequent to a charge period. The difference voltage capacitor charging circuit may perform the elimination of the common mode voltage simultaneously with a differential to single-ended conversion by connecting one node of the capacitor to a constant voltage. The difference voltage capacitor charging circuit may couple two nodes of the capacitor respectively to single-ended amplifiers.
The capacitor network may implement PRD. The receiver may apply feedback for the elimination of the common mode voltage to outputs of two single-ended amplifiers to which signals from the capacitor network are input. The capacitor network may include two or more coupling capacitors, and the coupling capacitors are connected in parallel during a precharge period and in series during a decision period.
According to the present invention, there is provided a receiver comprising an input line via which an input signal is supplied; a plurality of sample-and-hold circuits for sequentially latching the input signal by a multi-phase periodic clock, and for holding the latched input signal; and a decision circuit for making a decision on the input signal by generating a signal corresponding to a weighted sum of the outputs of the sample-and-hold circuits, wherein an output valid period of each sample-and-hold circuit is made longer than one bit time of the input signal; and the decision circuit is operated by using the weighted sum generated during a period where the output valid period of the sample-and-hold circuit overlaps the output valid period of another sample-and-hold circuit operating before or after the sample-and-hold circuit.
The decision circuit may generate a voltage, current, or charge signal corresponding to the weighted sum of the outputs of the sample-and-hold circuits. An operating cycle of the sample-and-hold circuit may be set equal to two bit times of the input signal; and a sample period of the sample-and-hold circuit may be made longer than a hold period thereof, thereby making the output valid period of the sample-and-hold circuit overlap the output valid period of another sample-and-hold circuit operating before or after the sample-and-hold circuit. An operating cycle of the sample-and-hold circuit may; be set equal to three or more bit times of the input signal, and the output valid period of the sample-and-hold circuit is set equal to or longer than one bit time of the input signal.
The weighted sum of the outputs of the sample-and-hold circuits may be generated by converting the output signals of the sample-and-hold circuits into currents by a transconductor using transistors, and by passing the currents into a common load device. The weighted sum may be adjusted by varying the number of transistors to be connected in parallel in the transconductor. A weight in the weighted sum may be adjusted by varying a current bias value in the transconductor.
The decision circuit may generate the signal corresponding to the weighted sum of the outputs of the sample-and-hold circuits by interconnecting capacitors each charged to a hold voltage. The decision circuit may generate the weighted sum based on differences in charges stored in the capacitors. The decision circuit may generate the signal corresponding to the weighted sum of the outputs of the sample-and-hold circuits by moving charges corresponding to the outputs of the sample-and-hold circuits into a common capacitor through a charge transfer circuit. The weighted sum may be adjusted by varying the number of transistors to be connected in parallel in the charge transfer circuit.
Further, according to the present invention, there is provided a transceiver circuit comprising a driver for outputting a transmit signal onto a signal transmission line; a receiver for receiving a receive signal from the signal transmission line; and a compensation voltage generating circuit for generating a compensation voltage used to compensate for an interference voltage caused by the driver, and for supplying the compensation voltage to the receiver, wherein bidirectional signal transmission is performed by controlling an output level of the compensation voltage generating circuit in accordance with the phase relationship between the transmit signal and the receive signal.
The driver may be a constant-current driver. The driver may include a first driver unit array having a plurality of constant-current driver units; and a second driver unit array having a plurality of constant-current driver units, transmit signals being sequentially output by switching between the first and second driver unit arrays. Each of the driver unit arrays may control the operating condition of the plurality of constant-current driver units in each driver unit array and thereby may adjust a transient characteristic of the transmit signal. The transceiver circuit may further comprise a predriver for driving each of the driver unit arrays, wherein the predriver may be driven by a 4n-phase clock whose cycle is twice as long as bit time T, where n denotes the number of driver units in each driver unit array.
The compensation voltage generating circuit may be a replica driver having the same circuit configuration as that of the driver and driven by the same data as that for the driver, and may include a unit for controlling the output amplitude and transient time of the replica driver. The driver may comprise a plurality of driver units, and the replica driver may be similar in configuration to one of the driver units constituting the driver. The compensation voltage generating circuit may further include a correction circuit for generating, based on a past output bit, a correction signal for improving the accuracy of the compensation voltage at decision timing in the receiver.
The compensation voltage generating circuit may generate the compensation voltage based on a data sequence consisting of the present bit and past bit of the transmit signal output from the driver and in accordance with the phase relationship between the transmit signal and the receive signal. The transceiver circuit may further comprise a unit for determining prior to actual signal transmission a compensation voltage for a boundary across which a decision in the receiver changes from data xe2x80x9c0xe2x80x9d to data xe2x80x9c1xe2x80x9d or from data xe2x80x9c1xe2x80x9d to data xe2x80x9c0xe2x80x9d, by transmitting a test pattern from the driver at one end while setting an output current level at zero in the driver at the other end; and a unit for storing the determined compensation voltage, and wherein actual signal transmission may be performed using the stored compensation voltage.
The compensation voltage generating circuit may include a plurality of compensation voltage correction circuits each for generating a voltage level that depends on a data sequence consisting of the present bit and past bit of the transmit signal output from the driver and on the phase difference between the transmit signal and the receive signal; and a selection circuit for selecting the output of one of the plurality of compensation voltage correction circuits in accordance with the data sequence.
A compensation offset value may be determined based on the value of a bit sequence of n past bits including the present bit, and wherein the transceiver circuit may include 2n receivers corresponding to 2n kinds of compensation voltages and a selection circuit for selecting a receiver output corresponding to an actual bit sequence. The transceiver circuit may further comprise an equalization circuit, provided for the driver or the receiver or for both the driver and the receiver, for compensating for a characteristic of the signal transmission line, and wherein the compensation voltage generating circuit may include a unit for receiving a test pattern and adjusting so as to minimize an interference value from the driver at the same end and intersymbol interference introduced into a, signal transmitted from the driver at the opposite end. The transceiver circuit may further comprise an impedance holding circuit for holding an output impedance of the driver at a constant value. The transient time of the transmit signal output from the driver may be set substantially equal to bit time T.
According to the present invention, there is also provided a signal transmission system comprising a first transceiver circuit, a second transceiver circuit, and a signal transmission line connecting between the first and second transceiver circuits, wherein at least one of the first and second transceiver circuits is a transceiver circuit comprising a driver for outputting a transmit signal onto a signal transmission line; a receiver for receiving a receive signal from the signal transmission line; and a compensation voltage generating circuit for generating a compensation voltage used to compensate for an interference voltage caused by the driver, and for supplying the compensation voltage to the receiver, wherein bidirectional signal transmission is performed by controlling an output level of the compensation voltage generating circuit in accordance with the phase relationship between the transmit signal and the receive signal.
Further, according to the present invention, there is also provided a signal transmission method, having a driver for outputting a transmit signal onto a signal transmission line and a receiver for receiving a receive signal from the signal transmission line, in which a compensation voltage used to compensate for an interference voltage caused by the driver is generated and supplied to the receiver, wherein bidirectional signal transmission is performed by controlling the level of the compensation voltage in accordance with the phase relationship between the transmit signal and the receive signal.
The compensation voltage may be generated based on a data sequence consisting of the present bit and past bit of the transmit signal output from the driver and in accordance with the phase relationship between the transmit signal and the receive signal. A compensation voltage for a boundary across which a decision in the receiver changes from data xe2x80x9c0xe2x80x9d to data xe2x80x9c1xe2x80x9d or from data xe2x80x9c1xe2x80x9d to data xe2x80x9c0xe2x80x9d may be determined prior to actual signal transmission by transmitting a test pattern from the driver at one end while setting an output current level at zero in the driver at the other end, the determined compensation voltage may be stored in memory, and actual signal transmission may be performed using the stored compensation voltage. Transient time of the transmit signal output from the driver may be set substantially equal to bit time T.